Month: April 2022

High performance adiabatic computing systems will need an engineered powertrain, which will be new technology given that current adiabatic demonstrations are too small to reveal important issues. This will be true even if the high performance computer is a quantum computer.

Technology issues

Todays high performance computing systems dissipate around 200 W per chip. For high performance computers, the objective is more performance for the same 200 W per chip, not lower power chips.

Reversible circuits use multiple AC power-clocks. If the chip is running at 200 W per chip, the power-clock generators will need to be far enough away from the chip to avoid excessive dissipation in a small volume causing cooling difficulties. Hence, a separation will be required between the power-clock generators and the chip, as shown in the figure below.

CMOS microprocessors require clock waveforms to be generated within a few centimeters of the chip to avoid waveform distortion. However, reversible systems send power over the AC power-clock conductors, which carry a lot of power hence require a larger separation than just microprocessor clock lines. In conjunction with requirements for a precise waveforms, both classical and quantum system analyses [ZF008] indicate that the power-clock conductors are long enough that transmission line effects need to be considered, i. e. characteristic impedance and reflections.

In summary, document [ZF008] describes how the power-clock generators must launch predistorted power-clocks into the transmission lines such that they arrive the with the desired waveform.

Document [ZF008] also describes how the load presented by the chip affects the proper predistortion, and how different circuit families and design techniques can reduce load variance. Some design techniques inevitably case load variance, such as turning clocks to unused portions of the circuit on and off. The document describes how power-clock generators can change their predistorted waveform in anticipation of changes in chip load.

The page http://revcomp.org/optimal-ramps further describes how the linear ramp waveform frequently found in the literature is a good starting point but the lowest dissipation shape is flatter in the middle (an “s” shape). The overall result is that predistortion needs to be applied to the “s” shape, not a linear ramp.

The a single shift register stage places very little loading on a 50 Ohm coax and produces little distortion. While a single shift register stage may be easy to simulate in Spice, it is not representative of a high performance computer. Scaling the shift register length to 5,000 stages is more representative of a scaled up system, but the circuit is too big for Spice simulation. To address these issues, the script in appendix of [ZF008] scales transmission line parameters. Multiplying the characteristic impedance by 5,000 in a Spice simulation model yields the same voltage waveform as multiplying the number of shift register stages. See [ZF008] for details.

Code

The script in [ZF008] simulates driving a circuit with predistortion to compensate for transmission line distortion.

Open research topics

Say you are tasked to make an ASIC for a computational accelerator and you have the ability to create a CMOS chip that can dissipate 200 W. The task is to asses the feasibility using reversible logic circuits, yet still using the same CMOS process. Based on the figure above, say the power-clocks will drive 2,000 W into the chip of which 1,800 W comes out. That leaves the 200 W dissipation, so you will not have to change the chip’s cooling.

First, engineer the power-clocks and figure out how to cool them. This will give an estimate of the volume required by the power-clock generators and 2,000 W of heat exchangers. This will then give an idea of how long the cables will be and hence the impact of cable RF losses and reflections. Then figure out the predistorted waveform, starting with the objective of a predistortion to yield a linear ramp and then a predistortion for an optimized waveform.

The second topic is to repeat the task above for a 4 K stage in a quantum computer. Say the quantum computer needs a 1 MHz clock, which will determine the fraction of energy dissipated versus ejected. From this, engineer room-temperature power-clocks and the wiring to get the signals to the 4 K stage. This wiring will be longer than the previous example because they will have to pass through a cryostat boundary. Include filtering for extra credit. Figure out the predistorted waveform for both linear optimized waveforms at the chip.

References

[ZF008] Erik DeBenedictis. Energy Management for Adiabatic Circuits. Zettaflops, LLC Technical Report ZF008, v1.2, April 15, 2021 https://www.debenedictis.org/erik/CATC/EMgt4Adia-ZF008-v1.2.pdf.

Additional information

The literature almost universally depicts reversible logic clocks with linear rising and falling segments, yet ramps that are flatter in the middle dissipate less. The reason for linear ramps that the simplest explanation of adiabatic behavior assumes transistors have a fixed R_on when conducting, and linear ramps have the lowest dissipation when R_on is constant. The simplest explanation is given first.

Technology issues

R_on actually decreases with larger forward bias on the gate, and behavior is further complicated by saturation. The lowest forward bias is at the middle of the swing, or the midpoint of the ramp.

In simple terms, the best waveform rises quickly when the transistor is on strongly or off, but needs to slow down when the resistance is higher to avoid I²R losses.

Code

Ramps are described in this software as having unit width and height, so the baseline linear ramp goes from (t=0, v=0) to (t=1, v=1). Pretty good ramps can be created by dividing the unit time into five linear sub ramps of length .2. With two parameters, h1 and h2 (h for height), the segmented ramp will go through the following points: (t=0, v=0), (t=.2, v=h1), (t=.4, v=h2), (t=.6, h=1-h2), (t=.8, h=1-h1), (t=1, v=1).

In developing software on this site, it was found that dissipation can be reduced by around 30% through proper ramp shape, with 5 segments adequate to get within about 1% of optimal.

For many circuits, the parameters o1=.20 h1=.34 o2=.40 h2=.46 are a good starting point. H1 and h2 can be fine tuned by optimization. For additional generality, the time divisions are defined by statements o1=.2 and o2=.4 (o for offset), although this is not necessary in most cases..