Some of my colleagues have expressed interest in the sizing of transistors in reversible logic, so I am posting the result of some simulations I performed in late 2021.
I am posting a PowerPoint at the bottom of this page with simulation output and an explanation. The file is intended to be viewed as an build-up type animation that shows the effect of widening transistors.
Summary of technical issue
CMOS design first and foremost widens transistors to meet timing closure.
Reversible circuits are supposed to be low power, so the baseline assumption is that you should use minimum size transistors everywhere. Such a reversible circuit all will function correctly, but it will not have the lowest dissipation because drops across some of the small transistors will have quadratically growing V2/R losses. So, the lowest energy solution involves making some transistors wider.
Reversible circuits need wider transistors in about the same places as CMOS circuits, namely when driving large capacitive loads or long wires. However, the large transistors reduce dissipation rather than maximize speed. There is an optimal size for both reversible and CMOS transistors, which is where the gate capacitance is about equal to wire capacitance. Gate capacitance larger than this amount causes CMOS to run slower and reversible to dissipate more.
Device variance will cause a reversible gate to dissipate more than the expected amount, but it will still function correctly. This is a better outcome than variance causing a CMOS gate to become slower than expected, miss the setup time of the next latch, and cause data corruption.
Simulation and explanation
The PowerPoint below shows the dissipation of a shift register with a 10 fF wire load. Transistor width is 360 nm, 720 nm, 1.44 μm, 2.88, and μm 5.76 μm. One sees that the reversible advantages shifts to a higher frequency as the transistor becomes wider.