Generating sine waves in quadrature
Resonators generate sine waves directly, but maintaining a 90˚ relative phase between the power-clocks becomes a challenge. Past work tended to use four independent waveform generators initialized with phases in progressive multiples of 90˚. The phase relationship stayed constant due to precise frequency control or synchronization.
To illustrate the problem, say one of the power-clocks misses its intended frequency by 1 Hz. After ¼ of a second, its waveform will align with one of the neighboring waveforms. This would cause the reversible logic circuits to run incorrectly, potentially in reverse.
The solution would be to find a type of resonator that naturally oscillates as four sine waves with phases in progressive multiples 90˚.
This post introduces the circuit shown in Fig. 1, called 4LC, and derived from the lumped-element transmission line shown in Fig. 1a. Sine waves propagate without loss in both directions up to a maximum frequency or minimum wavelength. Due to its lumped circuit nature, we must measure wavelength in circuit stages rather than distance.
Fig. 1b shows the lumped-element transmission line connected into a cycle. Subject to frequency or wavelength limits, the cyclic circuit will carry periodic waveforms independently in both directions. However, the period of sine waves making up a periodic waveform (i.e. Fourier decomposition) must be an integral fraction of the waveform’s period. The allowable integers are zero and one in the four-stage lumped transmission line. Zero corresponds to DC and one corresponds to a sine wave whose wavelength is four stages.
The lumped transmission line model helped explain properties of the four-stage circuit, but we will subsequently consider the 4LC circuit to be four inductors and four capacitors as illustrated in Fig. 1b. We know from transmission line analysis that 4LC has two oscillation modes, one looking like four-phase power-clocks and the other comprising the same waveforms propagating backwards.
The 4LC circuit has oscillation modes, each characterized by a frequency and an amount of energy. Theoretically, the 4LC circuit is lossless and would oscillate forever. However, losses in the 2LAL circuit cause the total energy to decrease over time, including loss of energy in oscillation modes plus crosstalk between modes.
We now explain the 4LC circuit’s parasitics for completeness. Since the 4LC circuit has eight components, each with one state variable, the modes must span eight degrees of freedom. A general eigenvalue and eigenvector analysis appears in the next section, but circuit symmetries allow a less mathematical solution here.
The reversible logic clocks in each direction have amplitude and phase, consuming four degrees of freedom. A DC offset consumes a fifth (a DC offset of Vp/2 positions the sine wave between GND and Vp). A circulating current in the inductors consumes a sixth (which can be important for superconductor implementations). A parasitic mode discussed below accounts for the remaining two.
Moving the 4LC circuit components to different positions in Fig. 1c reveals a line of symmetry. Due to symmetry, initializing the two halves of the circuit identically would lead to time evolution where the voltages on (P0, P2) and (P1, P3) remain the same forever. Putting wires between nodes that have equal voltages will not alter behavior, so we can turn the dashed lines P0-P2 and P1-P3 into wires and simplify the circuit. Simplification merges four parallel inductors into a single inductor of ¼ the inductance. Four capacitors appear in series-parallel combination that simplifies to a single capacitor. Thus, the circuit’s behavior will be equivalent to an LC circuit with the same capacitance but ¼ the inductance. This mode will oscillate with frequency 2fLC. This parasitic mode has two degrees of freedom representing amplitude and phase. In summary, the frequencies discussed differ by multiples of √2:
- fLC = 1 / (2π √LC): textbook expression for the resonance of an LC circuit
- √2 ∙ fLC: the 4lc mode used for reversible logic clocks,
- 2fLC: the additional parasitic mode
State space analysis
The author chose the 4LC circuit by visualizing circuit networks, yet circuit visualization does not reveal certain engineering details. For example, visualization will not reveal the effect of an out-of-tolerance inductor. However, state space analysis reveals such quantitative effects. This section outlines how to obtain additional quantitative detail, but the reader could consult an engineering textbook for further details.
As mentioned previously, an LC circuit has separate degrees of freedom, or independent variables, for the current in each inductor and the voltage on each capacitor. As identified on the top row of the table below, we say xi, i=0…3 is a variable representing the current in inductor Li, and xi+4, i=0…3 is a variable representing the voltage on capacitor Ci. In mathematical notation, a dot over a variable, such as ẋ, represents time derivative, so ẋi, i=0…3 is the time derivative of current xi, so Liẋi is the voltage across inductor Li, based on the equation for voltage across an inductor. Likewise, ẋi+4, i=0…3 is the time derivative of voltage xi+4, and Ciẋi is the current through capacitor Ci.
| x0= I(L0) | x1= I(L1) | x2= I(L2) | x3= I(L3) | x4= V(C0) | x5= V(C1) | x6= V(C2) | x7= V(C3) | |
| L0ẋ0 = | 1x4 | −1x7 | ||||||
| L1ẋ1 = | −1x4 | +1x5 | ||||||
| L2ẋ2 = | −1x5 | +1x6 | ||||||
| L3ẋ3 = | −1x6 | +1x7 | ||||||
| C0ẋ0 = | −1x0 | +1x1 | ||||||
| C1ẋ1 = | −1x1 | +1x2 | ||||||
| C2ẋ2 = | −1x2 | +1x3 | ||||||
| C3ẋ3 = | 1x0 | −1x3 |
Reading across each row in the table yields an equation based on the topology of the 4lc circuit. For example, L0ẋ0 is the voltage across inductor L0, whose ends connect to C3 and C0, so the voltage across the inductor is the C0 voltage x4 minus the C3 voltage x7.
The reader will see that all columns (except the first column, which has row labels) include a 1 or −1 coefficient and a term xi, where i is the column number (minus one, if we count the column of row labels). The coefficients in the table above form the matrix below. The reader should be able to tie the table to a matrix in an engineering textbook.
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | −1 |
| 0 | 0 | 0 | 0 | −1 | 1 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | −1 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | −1 | 1 |
| −1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | −1 | 1 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | −1 | 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 0 | −1 | 0 | 0 | 0 | 0 |
Decomposing the matrix into eigenvalues and eigenvectors is the next step. For this, the reader may use https://matrixcalc.org/vectors.html. The eigenvalues represent the frequency of the eight oscillation modes, of which
- two have frequency zero, corresponding to DC offset and the current circulating in the inductors,
- four have frequency ±√2, corresponding to the amplitude of the reversible logic clocks (as sine and cosine waves) propagating in forward and reverse directions, and
- two have frequency 2, corresponding to the amplitude of the parasitic mode (as sine and cosine waves).
Approachable instructions on computing the relevant eigenvalues are as follows. Go to https:/jj-2025-full-text, expand the matrix to 8×8 using the + button, enter the values as shown in Fig 2, then click “singular value decomposition” (SVD).
The result will be four matrices. The third matrix is diagonal and contains the eigenvalues, as shown in Fig. 3.
The eigenvectors are a bit more difficult to decipher, but can be seen in the fourth matrix, as shown in Fig. 4.
Each column contains one oscillation mode, with the current voltages at the top and the four voltages below.
The middle four columns represent the propagating modes. The fifth column contains voltage values (-√2/2, 0, √2/2, 0). Reduced to just negative, 0, positive, the pattern is (-, 0, +, 0), which is the pattern for a negative cosine wave across the four capacitors. The fifth column contains voltage values (0, -√2/2, 0, √2/2), which is a negative sine wave. The third and fourth column just contain initial currents for the inductors.
Since there are four equal eigenvalues, the SVD produces a valid basis set, but not necessarily the basis set we want. So, we have to create combinations of the columns provided by SVD. In this case, the fifth column ± plus or minus the difference between the third and fourth will make the negative cosine wave propagate backward or forward. Similarly, for the sixth column and its negative sine wave. With this combination, we have turned the result of SVD into sine and cosine waves that propagate backwards and forwards.
Note that the output of an SVD algorithm is not uniquely defined when there are duplicated eigenvalues, so a different implementation of the SVD algorithm could produce different values for columns three to six.
The seventh and eighths columns correspond to a zero eigenvalue, or DC values. The seventh column specifies inductors with equal currents, so it is the circulating current. The eighth column specifies capacitors with equal voltages, so it is the DC offset.
The first two columns are the high frequency parasitic. The eigenvalues are sine and cosine waves, which can be considered a sine wave plus phase.
Changing the 1’s in the first row to 1.01 effectively changes the value of L0, leading to slightly different frequencies and waveforms. Likewise for capacitors. Notably, the mathematics shows a change in the overall frequency while maintaining the clock-to-clock phase.
Other circuits are possible. For example, a 12-stage lumped element transmission line could reproduce the 4lc but also allow tailoring of the waveform by adding a third harmonic. At the price of higher complexity in power-clock generation, the tailored waveform could lead to higher energy efficiency from the same circuit.