The literature almost universally depicts reversible logic clocks with linear rising and falling segments, yet ramps that are flatter in the middle dissipate less. The reason for linear ramps that the simplest explanation of adiabatic behavior assumes transistors have a fixed Ron when conducting, and linear ramps have the lowest dissipation when Ron is constant. The simplest explanation is given first.
Technology issues
Ron actually decreases with larger forward bias on the gate, and behavior is further complicated by saturation. The lowest forward bias is at the middle of the swing, or the midpoint of the ramp.
In simple terms, the best waveform rises quickly when the transistor is on strongly or off, but needs to slow down when the resistance is higher to avoid I2R losses.
Code
Ramps are described in this software as having unit width and height, so the baseline linear ramp goes from (t=0, v=0) to (t=1, v=1). Pretty good ramps can be created by dividing the unit time into five linear sub ramps of length .2. With two parameters, h1 and h2 (h for height), the segmented ramp will go through the following points: (t=0, v=0), (t=.2, v=h1), (t=.4, v=h2), (t=.6, h=1-h2), (t=.8, h=1-h1), (t=1, v=1).
In developing software on this site, it was found that dissipation can be reduced by around 30% through proper ramp shape, with 5 segments adequate to get within about 1% of optimal.
For many circuits, the parameters o1=.20 h1=.34 o2=.40 h2=.46 are a good starting point. H1 and h2 can be fine tuned by optimization. For additional generality, the time divisions are defined by statements o1=.2 and o2=.4 (o for offset), although this is not necessary in most cases..