Resonators generate sine waves directly, but maintaining a 90˚ relative phase between the power-clocks becomes a challenge. Past work tended to use four independent waveform generators initialized with phases in progressive multiples of 90˚. The phase relationship stayed constant due to precise frequency control or synchronization.
To illustrate the problem, say one of the power-clocks misses its intended frequency by 1 Hz. After ¼ of a second, its waveform will align with one of the neighboring waveforms. This would cause the reversible logic circuits to run incorrectly, potentially in reverse.
The solution would be to find a type of resonator that naturally oscillates as four sine waves with phases in progressive multiples 90˚.
This post introduces the circuit shown in Fig. 1, called 4LC, and derived from the lumped-element transmission line shown in Fig. 1a. Sine waves propagate without loss in both directions up to a maximum frequency or minimum wavelength. Due to its lumped circuit nature, we must measure wavelength in circuit stages rather than distance.
Fig. 1. Schematic of the 4lc circuit. (a) A lumped element transmission line, (b) four-stage cycle, (c) symmetry revealing a parasitic mode.
Fig. 1b shows the lumped-element transmission line connected into a cycle. Subject to frequency or wavelength limits, the cyclic circuit will carry periodic waveforms independently in both directions. However, the period of sine waves making up a periodic waveform (i.e. Fourier decomposition) must be an integral fraction of the waveform’s period. The allowable integers are zero and one in the four-stage lumped transmission line. Zero corresponds to DC and one corresponds to a sine wave whose wavelength is four stages.
The lumped transmission line model helped explain properties of the four-stage circuit, but we will subsequently consider the 4LC circuit to be four inductors and four capacitors as illustrated in Fig. 1b. We know from transmission line analysis that 4LC has two oscillation modes, one looking like four-phase power-clocks and the other comprising the same waveforms propagating backwards.
The 4LC circuit has oscillation modes, each characterized by a frequency and an amount of energy. Theoretically, the 4LC circuit is lossless and would oscillate forever. However, losses in the 2LAL circuit cause the total energy to decrease over time, including loss of energy in oscillation modes plus crosstalk between modes.
We now explain the 4LC circuit’s parasitics for completeness. Since the 4LC circuit has eight components, each with one state variable, the modes must span eight degrees of freedom. A general eigenvalue and eigenvector analysis appears in the next section, but circuit symmetries allow a less mathematical solution here.
The reversible logic clocks in each direction have amplitude and phase, consuming four degrees of freedom. A DC offset consumes a fifth (a DC offset of Vp/2 positions the sine wave between GND and Vp). A circulating current in the inductors consumes a sixth (which can be important for superconductor implementations). A parasitic mode discussed below accounts for the remaining two.
Moving the 4LC circuit components to different positions in Fig. 1c reveals a line of symmetry. Due to symmetry, initializing the two halves of the circuit identically would lead to time evolution where the voltages on (P0, P2) and (P1, P3) remain the same forever. Putting wires between nodes that have equal voltages will not alter behavior, so we can turn the dashed lines P0-P2 and P1-P3 into wires and simplify the circuit. Simplification merges four parallel inductors into a single inductor of ¼ the inductance. Four capacitors appear in series-parallel combination that simplifies to a single capacitor. Thus, the circuit’s behavior will be equivalent to an LC circuit with the same capacitance but ¼ the inductance. This mode will oscillate with frequency 2fLC. This parasitic mode has two degrees of freedom representing amplitude and phase. In summary, the frequencies discussed differ by multiples of √2:
fLC = 1 / (2π √LC): textbook expression for the resonance of an LC circuit
√2 ∙ fLC: the 4lc mode used for reversible logic clocks,
2fLC: the additional parasitic mode
State space analysis
The author chose the 4LC circuit by visualizing circuit networks, yet circuit visualization does not reveal certain engineering details. For example, visualization will not reveal the effect of an out-of-tolerance inductor. However, state space analysis reveals such quantitative effects. This section outlines how to obtain additional quantitative detail, but the reader could consult an engineering textbook for further details.
As mentioned previously, an LC circuit has separate degrees of freedom, or independent variables, for the current in each inductor and the voltage on each capacitor. As identified on the top row of the table below, we say xi, i=0…3 is a variable representing the current in inductor Li, and xi+4, i=0…3 is a variable representing the voltage on capacitor Ci. In mathematical notation, a dot over a variable, such as ẋ, represents time derivative, so ẋi, i=0…3 is the time derivative of current xi, so Liẋi is the voltage across inductor Li, based on the equation for voltage across an inductor. Likewise, ẋi+4, i=0…3 is the time derivative of voltage xi+4, and Ciẋi is the current through capacitor Ci.
x0=I(L0)
x1=I(L1)
x2=I(L2)
x3=I(L3)
x4=V(C0)
x5=V(C1)
x6=V(C2)
x7=V(C3)
L0ẋ0 =
1x4
−1x7
L1ẋ1 =
−1x4
+1x5
L2ẋ2 =
−1x5
+1x6
L3ẋ3 =
−1x6
+1x7
C0ẋ0 =
−1x0
+1x1
C1ẋ1 =
−1x1
+1x2
C2ẋ2 =
−1x2
+1x3
C3ẋ3 =
1x0
−1x3
Reading across each row in the table yields an equation based on the topology of the 4lc circuit. For example, L0ẋ0 is the voltage across inductor L0, whose ends connect to C3 and C0, so the voltage across the inductor is the C0 voltage x4 minus the C3 voltage x7.
The reader will see that all columns (except the first column, which has row labels) include a 1 or −1 coefficient and a term xi, where i is the column number (minus one, if we count the column of row labels). The coefficients in the table above form the matrix below. The reader should be able to tie the table to a matrix in an engineering textbook.
0
0
0
0
1
0
0
−1
0
0
0
0
−1
1
0
0
0
0
0
0
0
−1
1
0
0
0
0
0
0
0
−1
1
−1
1
0
0
0
0
0
0
0
−1
1
0
0
0
0
0
0
0
−1
1
0
0
0
0
1
0
0
−1
0
0
0
0
Decomposing the matrix into eigenvalues and eigenvectors is the next step. For this, the reader may use https://matrixcalc.org/vectors.html. The eigenvalues represent the frequency of the eight oscillation modes, of which
two have frequency zero, corresponding to DC offset and the current circulating in the inductors,
four have frequency ±√2, corresponding to the amplitude of the reversible logic clocks (as sine and cosine waves) propagating in forward and reverse directions, and
two have frequency 2, corresponding to the amplitude of the parasitic mode (as sine and cosine waves).
Approachable instructions on computing the relevant eigenvalues are as follows. Go to https:/jj-2025-full-text, expand the matrix to 8×8 using the + button, enter the values as shown in Fig 2, then click “singular value decomposition” (SVD).
Fig. 2. Computing eigenvalues and eigenvalues (singular value decomposition) of the 4LC circuit.
The result will be four matrices. The third matrix is diagonal and contains the eigenvalues, as shown in Fig. 3.
Fig. 3. 4LC Eigenvalues.
The eigenvectors are a bit more difficult to decipher, but can be seen in the fourth matrix, as shown in Fig. 4.
Fig. 4. 4LC Eigenvectors.
Each column contains one oscillation mode, with the current voltages at the top and the four voltages below.
The middle four columns represent the propagating modes. The fifth column contains voltage values (-√2/2, 0, √2/2, 0). Reduced to just negative, 0, positive, the pattern is (-, 0, +, 0), which is the pattern for a negative cosine wave across the four capacitors. The fifth column contains voltage values (0, -√2/2, 0, √2/2), which is a negative sine wave. The third and fourth column just contain initial currents for the inductors.
Since there are four equal eigenvalues, the SVD produces a valid basis set, but not necessarily the basis set we want. So, we have to create combinations of the columns provided by SVD. In this case, the fifth column ± plus or minus the difference between the third and fourth will make the negative cosine wave propagate backward or forward. Similarly, for the sixth column and its negative sine wave. With this combination, we have turned the result of SVD into sine and cosine waves that propagate backwards and forwards.
Note that the output of an SVD algorithm is not uniquely defined when there are duplicated eigenvalues, so a different implementation of the SVD algorithm could produce different values for columns three to six.
The seventh and eighths columns correspond to a zero eigenvalue, or DC values. The seventh column specifies inductors with equal currents, so it is the circulating current. The eighth column specifies capacitors with equal voltages, so it is the DC offset.
The first two columns are the high frequency parasitic. The eigenvalues are sine and cosine waves, which can be considered a sine wave plus phase.
Changing the 1’s in the first row to 1.01 effectively changes the value of L0, leading to slightly different frequencies and waveforms. Likewise for capacitors. Notably, the mathematics shows a change in the overall frequency while maintaining the clock-to-clock phase.
Other circuits are possible. For example, a 12-stage lumped element transmission line could reproduce the 4lc but also allow tailoring of the waveform by adding a third harmonic. At the price of higher complexity in power-clock generation, the tailored waveform could lead to higher energy efficiency from the same circuit.
Abstract—Researchers developed about a dozen semiconductor reversible (or adiabatic) logic chips since the early 1990s, validating circuit designs and proving the concept—but scale up required a further advance. This document shows that cryogenic inductors made of a new High Kinetic Inductance (HKI) material provide the advance. This material can be deposited as an integrated circuit layer, where it has enough energy recycling capacity to power a reversible circuit of the same size. This allows a designer to replicate and scale a complete reversible logic subsystem in accordance with Moore’s law.
Keywords—reversible logic; adiabatic logic; reversible computing; 2LAL; energy recycling power supply; CMOS; power-clocks; resonator; inductor; high kinetic inductance (HKI); YBCO; superinductor; intellectual property (IP)
I. Executive Summary
Reversible logic circuits created with funding from DARPA1 and others used energy recycling to raise the energy efficiency of logic above CMOS levels, yet extending these efficiency gains to the chip level requires a scalable energy recycling power supply for the circuits. With the recent availability of HKI inductors for the power supply, it is now possible to create much more energy efficient quantum computer control chips for operation at 4 K, essentially by replacing the gates in cryo CMOS circuits (e.g. Horse Ridge2) with reversible circuits of higher energy efficiency, thus enabling more qubits before exceeding cryocooler capacity. This opportunity also applies to Read Out Integrated Circuits (ROICs), or sensors with in situ data processing.
HKI inductors now available operate at 4 K and below, but the approach may extend to 77 K using high-Tc superconducting inductors, such as Yttrium barium copper oxide (YBCO).3-4 Thus, this approach may apply to DARPA’s Low Temperature Logic Technology (LTLT) program,5 which is exploring energy efficiency improvements for a broad range of applications in a cryogenic data center.
MIT-LL6 demonstrated a hybrid monolithic foundry process with semiconductors (CMOS) and a Josephson junction process including HKI, while SeeQC7 developed the HKI process used as an example in this document.
As a next step, this document suggests a scale up test of self–contained reversible logic IP (“intellectual property,” which is a term of art in the semiconductor field for chip layout geometry), including CMOS-converted-to-reversible semiconductor circuits as a base and a superconducting layer that includes HKI. This IP would not require an additional energy recycling power supply, but could be AC-powered like three–phase electrical power transmission (but two- or four-phases at a lower voltage and higher frequency).
Multiple units of such IP could be laid out next to each other on a chip, leading to scalability rules similar to integrated circuits—rather than the less attractive scalability rules that apply to 3D structures—as was the case with previous reversible logic projects.
II. Introduction
This document uses the result of a recent materials science advance called High Kinetic Inductance (HKI) to make reversible logic scalable. DARPA funded reversible logic in the early 1990s,1 leading to about a dozen projects creating “successful” test chips. While successful, the test chips did not lead to R&D for scale up testing. In retrospect, the problem was that there was no material available at the time that had the required speed, power density, and scalability for an essential component called the energy recycling power supply. With HKI, it is now possible to fabricate scalable hybrid semiconductor-superconductor chips containing both reversible logic and its unique power supply.
The benefit of reversible logic. CMOS operates on DC power, where energy enters a chip on a DC power wire and charges transistor gate capacitance and capacitance between signal wires. When a data value changes, the ½CV2 energy on the capacitance turns into heat within the chip. The CMOS approach therefore turns CV2 energy into heat for every signal change—and signal changes generally correspond to logic operations and are proxies for computational throughput.
The reversible logic approach uses an AC power supply. On the first half of each clock cycle, approximately the same amount of energy (½CV2) used by CMOS enters the chip, but a reversible logic chip returns almost all the energy on the second half of each cycle—thus decreasing wall-power energy consumption by factors in the range of 10x-1,000x.
The HKI advance. Most reversible logic R&D comprises reversible logic circuitry and a separate energy recycling power supply. A semiconductor foundry creates the logic circuit, which is scalable much like a CMOS chip, but the energy recycling power supply relies on a non-scalable component, such as an inductor elsewhere on a printed circuit board or in a 3D structure. In other cases, it is an integrated component, such as a spiral inductor, but which is much larger than the reversible circuitry it supports.
A single layer of HKI inductors has about the same energy density as a cryo semiconductor circuit (CMOS or reversible, which have about the same energy density), thus allowing the non-scalable component in the previous paragraph to become an additional layer right on top of a reversible circuit.
Potential impact. Reversible logic is like a “Moore’s law booster,” meaning it applies to the latest semiconductor process at any point in time, increasing energy efficiency over and above what Moore’s law provides. As such, reversible logic can increase performance within existing power envelopes or reduce power for the given application. Subject to cryogenic operating temperatures, reversible logic applies to applications that would otherwise use the latest version of CMOS.
With today’s technology, reversible logic applies to 4 K cryogenic systems, such as quantum computer control and integrated sensor arrays. There is a future path for high Tc, 77 K operation, such as the DARPA LTLT program.5
Potential scale-up test. This document is not intended as an R&D proposal, but the technology appears ready for a scale-up test comprising the following phases:
Create and test (1a) basic test structures for a cryo semiconductor chip interacting with HKI inductors of approximately the correct inductance and current handling capacity and (1b) an initial version of a reversible logic circuit powered by an external supply.
Demonstrate (2a) a second version of the reversible semiconductor circuit, now of a design sufficient to draw conclusions about the scalability of reversible logic in general, powered by (2b) a second set of HKI inductors optimized for the specific circuit (2a).
III. Technical Issues in Scaling up Reversible Logic
This section explains how a High Kinetic Inductance (HKI) material enables reversible logic scale up. For brevity, this document does not describe the underlying principles of reversible logic, but interested readers can read ref. 8.
Background. Athas,1 et. al. created, fabricated, and tested the AC-1 reversible microprocessor in the early 1990s under DARPA sponsorship, demonstrating increased energy efficiency over and above Moore’s law. One might have expected follow-on DARPA scale up testing, but there was none. Instead, other R&D groups tested about a dozen variants of the circuits used in the DARPA project, coining circuit family names such as SQRL,8 2LAL,9-10 RERL,11 S2LAL,12 Q2LAL,13 and others—but the author does not know of any scale up tests. The author’s position is that scale up required a physical science advance, so further circuit testing was destined to yield similar, unscalable results.
Power-clock background. Reversible logic uses energy recycling, as illustrated in Fig. 1. Past R&D on reversible circuits yielded many logic families, all with ramped 4- or 8-phase clocks. The 4-phase version illustrated in Fig. 1a is for 2LAL.9-10 As illustrated in Fig. 1c for the bottom clock waveform, energy moves into the reversible circuit during the rising edge of the clock. The energy mostly charges gate, wire-to-GND, and wire-to-wire capacitance. The capacitive energy moves back into the energy recycling power supply during the falling edge of the clock, and the cycle repeats using the recycled energy plus a small amount of wall plug power.
Fig. 1 (a) Ramped power-clocks, (b) sinusoidal power-clocks, (c) 4LC circuit, (d) module. Each phase is called a “tick.”
The efficiency of the energy recycling process depends on resistive losses in the semiconductor circuit, which rise with clock frequency. Excluding the energy recycling power supply (because this document offers an improvement), the recycling efficiency can be around 90% at the typical clock rate of room-temperature CMOS (~1 GHz), indicating an energy efficiency increase of 10x. At lower speeds, the recycling efficiency may be 99% or higher, corresponding 100x or more.
The ramped clocks in Fig 1a are for the reader’s convenience when accessing the large body of existing literature on reversible logic. In this document, the energy recycling power supply is just inductors, so the natural clocks are the sinusoidal waveforms in Fig. 1b. The reader will see the waveforms have the same basic shape – and the author’s tests indicate they both have about the same energy efficiency when powering reversible circuits.
Scale up story narrative. To understand scale up, we first need a few key facts about the solution in Fig. 2c. The solution will be to cover the reversible logic semiconductor circuitry (bottom) with one or more layers of HKI material (top). Lithographic patterning will divide the HKI material into inductors (shown as meanders) that connect pairs of clock phases through the vertical pillars (the figure is an exploded view; the pillars are of near-zero height). An external non-recycling waveform will drive the clocks, but will draw an order of magnitude less energy from the wall plug than enters the circuit via the pillars. This is the energy efficiency advantage.
Fig. 2. (a) Typical reversible logic test chip. Includes a “power-clock generator” but also requires external inductors. (b) Geometric inductors requiring empty space. (c) HKI inductors. Exploded view; actual fabrication would be monolithic.
Fig. 2a illustrates a typical scenario for previous R&D efforts.14 An R&D team created a reversible logic test chip as shown, in this case including a “power-clock generator” as identified by a blue arrow. Unfortunately, the R&D team was not funded for scale up testing even though the circuit testing was successful. The red arrow points to the problem, which is a tiny inductor symbol outside the chip. The chip may scale up according to Moore’s law, but the inductor does not. Furthermore, the R&D team did not label the tiny inductor as “future HKI inductor” because HKI material was too new.
Fig. 2b illustrates a higher temperature but more challenging option based on non-HKI (also called non-superconducting or “geometric”) inductors. These inductors require empty space to hold a magnetic field, such as the inside of a coil inductor or free space above and below an on-chip integrated spiral inductor (like the cloud in Fig. 2b). Since it is not possible to deposit “empty space” onto an integrated circuit, Fig. 2b is a 3D structure, which will not scale as well as predicted by Moore’s law.
Fig. 2b shows actual manufactured and tested YBCO inductors. These inductors and their foundry process are close to what is needed for reversible logic, see refs. 3-4 for details. While the 3D structure is not an integrated circuit, there are options for high Tc inductors,15 but they are beyond the scope of this document.
Fig. 2b also applies to normal metal (e.g. room temperature) electrical inductors. Aside from the 3D scalability issues just discussed, normal metal inductors are lossy at high frequencies. Further discussion of normal metal inductors is beyond the scope of this document.
We must now discuss how to implement Fig. 2c and show that an implementation can have sufficient energy capacity at speed.
Converting circuits from CMOS to scalable reversible logic. CMOS and reversible logic circuits are both comprise logic gates and wires, so a designer can replace CMOS logic circuits with the equivalent reversible logic circuits. This is not precisely true, but “true enough” for this argument. The reversible logic layout retains the long wires (e.g. busses) between groups of gates. Based on this imprecise argument, CMOS and reversible circuits will have about the same number of transistors and total wire length—hence the same amount of circuit capacitance and average energy flow during operation.
While the average energy flow rate is the same, the timing differs. Energy enters a CMOS circuit at a constant rate whereas Fig. 1c shows the energy entering the reversible circuit via power-clock φn during tick n (and leaving on tick n+2). The flow pattern for the sinusoidal clocks in Fig. 1b is conceptually the same but less distinct.
Numerically, the 4 mm x 4 mm Horse Ridge cryo CMOS qubit controller2 consumes 10-140 mW, or ECMOS = 62-875 mW/cm2. Based on the text, the range 10-140 mW corresponds to clock rates of f = 100 MHz-1.6 GHz.
The energy capacity per unit area of an HKI material has a simple formula, specifically ½L□Imax2, where L□ is the inductance per square of the process and Imax is the maximum current per unit wire width. (To be clear, cutting a square centimeter of HKI material into wires of 0.1 mm and 0.01 mm width yields inductors with different inductances but nearly the same energy capacity.) For the SeeQC process,7L□ = 8.5 pH/□, Ic = 2.5 mA/µm = 2500 A/m, so ½LI2 = 0.295 nW/cm2. At f = 1.6 GHz, Ereversible = 472 mW/cm2.
Based on rough numbers above, two layers of HKI inductor will suffice for powering a Horse Ridge-like chip converted to reversible logic.
State-of-the-art data center CPUs and accelerator chips have higher energy density and would require a hundred or more HKI layers. Theoretically, HKI inductors can operate in tall stacks like Flash memory, although tall HKI stacks are not currently manufacturable. HKI material is an active research area, so somebody might discover an HKI material with far higher energy density that would support high performance logic with fewer HKI layers.
Fabricating the necessary structure. Fig. 3 shows the baseline stack. The purple layers in Fig. 3a are an MIT-LL Josephson junction process stack (obtained from the internet) and the blue layers in Fig. 3b are the open source 130 nm Sky130 semiconductor process. After fabricating the semiconductor stack, the foundry planarizes the wafer and adds the superconductor stack using a Back End of Line (BEOL) process. Various foundries claim to have processes that are variants of Fig. 3, including MIT-LL.
Fig. 3. JCMOS for quantum applications (a) Back-End-Of-Line superconducting process on (b) standard CMOS process. (c) Novel THz or SFQ-capable via.
This document does not use Josephson junctions, but just HKI layers and vias, the latter shown in Fig. 3c. It is possible that hybrid chips for scale up testing could use the stack in Fig. 3a, but where an organization interested in Josephson junctions funds the development of the fabrication process. Once the process is available, enterprising chip designers can use it for other use cases, including this one.
Proof of design principle. We now know that HKI inductors have sufficient energy capacity, but we need a “proof of principle” that they will work in a plausible circuit. Fig. 2a needed to minimize the number of external inductors because they limited scalability, but this new design point can have as many lithographically defined inductors as will fit in the available space.
Fig. 4a illustrates the circuit concept, coined 4LC (4-ell-cee), comprising four inductors that naturally oscillate as four sine waves in quadrature as shown in Fig. 1b. Each of the four dotted squares in Fig. 4b effectively contains the circuit in Fig. 4a with each Pn = φn connected to the Cn capacitive loading of the Pn clock for the circuitry within the square. The array can be made as large as necessary, as long as the inductors around the boundary are applied in the pattern shown. The reader will note the absence of synchronization logic, high-current switches, and other complexities. The resonant modes of the LC array perform these functions naturally.
Fig. 4. (a) The 4lc quad resonator, which creates all four clocks at once with the correct phasing. (b) A potential design of the HKI layer, comprising a checkerboard of the quad resonators with clock phases labeled P0-P3. The array can extend to n x n and requires inductors double the value on the boundary as shown.
Simulation. The author created a simulation of the 4LC quad resonator in Fig. 4a, with the output appearing in Fig. 5.
For each plot in Fig. 5, the author entered the 4LC circuit into a circuit simulator, using initial conditions to create the sine waves in quadrature shown in Fig. 1b. The author then connected a 2LAL9-10 reversible logic circuit to the sine waves, and found that the circuits would initially function properly. The circuit’s function is to produce eight-phase clocks (as needed for several other reversible logic families), which are initially clean waveforms in the plots.
The 4LC circuit has oscillation modes, each characterized by a frequency and an amount of energy. Theoretically, the 4LC circuit is lossless and would oscillate forever. However, losses in the 2LAL circuit cause the total energy to decrease over time, including loss of energy in oscillation modes plus crosstalk between modes.
If the inductors and capacitors have low loss (i.e. the 4LC resonator has high Q), the circuit simulator will power the reversible logic for some time based on energy provided by the simulator’s initial conditions. The energy will decline over time, resulting in less amplitude in the sine waves and waveform distortion due to crosstalk. The “sine wave overlays” in Fig. 5a have two curves, the 4LC output values Pn and a simulator-generated reference wave. The reader can see the Pn amplitudes decline over time. As called out by the text “fails due to inadequate power” in Fig. 5a, the reversible logic circuit eventually produces a DC voltage. The remedy is to use external power to “top off” the energy in the desired oscillation mode while “draining out” undesired oscillation modes.
Fig. 5. Simulation of 4lc. (a) Works, runs down, and then fails. (b) “Topping off” allows continuous operation.
One way to “top off” the 4LC circuit would be to connect conventional sine waves, like those used in three-phase AC power, to the circuit through a resistor. The idea is that the resistor would transfer energy in or out of each oscillating mode until it matches the drive waveform’s amplitude and phase. This includes topping off the desired mode and draining the energy from other modes. The first plot in Fig. 5a uses a 15 KΩ drive resistor, but the resistor was too weak and the circuit failed. However, the second plot in Fig. 5b uses a stronger 5 KΩ resistor, topping off the circuit adequately and yielding consistent sine waves and eight-phase clocks across the chart.
The author used two forms of AC power. The first form was four-phase AC power (shown in Fig. 1a). The second form was two-phase AC power, with phases 90̊ from each other. The two-phase version requires just three wires, GND and the two phases.
Summary. Reversible logic has a long history, but progress stalled due to a missing but necessary physical science advance. This document explains the advance and suggests the time is right for scale up testing.
The document showed how a cryo CMOS-translated-to-reversible-logic circuit and one or two layers of HKI inductor, both of the same area, have about the same energy content and jointly form an energy-recycling power supply. Since the resulting structure is entirely defined by chip layout geometry for a hybrid process, the result scales as predicted by Moore’s law.
The document described and simulated a circuit called 4LC, which creates the four-phase energy recycling clocks used by 2LAL.9-10 A non-energy recycling AC power waveform drives the 4LC.
With today’s technology, reversible logic should be practical for 4 K cryogenic systems, such as quantum computer control and integrated sensor arrays. There is a future path for high Tc, 77 K operation, such as the LTLT program.
IV. Additional Information
The author has two additional files. If this publication (arXiv?) supports supplementary data, it will be added to this paper. The two files are:
A spreadsheet with equations for the top-level planning of reversible logic IP based on properties of the initial CMOS circuit and HKI parameters such as L□, Imax, and lithographic minimums for the width and space between HKI features. The spreadsheet explains how to scale the layout in Fig. 4b so the reversible logic operates at a specific clock rate—a topic not addressed in this document.
The ngspice simulation script that generated Fig. 5.
References
1. Athas, William C. “Energy-recovery CMOS.” Low Power Design Methodologies. Boston, MA: Springer US, 1996.
7. Yohannes, Daniel, et al. “Materials and methods for fabricating superconducting quantum integrated circuits.” U.S. Patent No. 11,991,935. 21 May 2024. https://patents.google.com/patent/US11991935B2/en.
8. Frank, Michael Patrick, and Thomas F. Knight Jr. Reversibility for efficient computing. Diss. Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999. https://dspace.mit.edu/handle/1721.1/9464.
9. Athas, W. C., et al. “A framework for practical low-power digital CMOS systems using adiabatic-switching principles.” International Workshop on Low Power Design. 1994.
14. Kim, Suhwan, Conrad H. Ziesler, and Marios C. Papaefthymiou. “A true single-phase 8-bit adiabatic multiplier.” Proceedings of the 38th annual Design Automation Conference. 2001.
15. Srivastava, Yogesh Kumar, et al. “The elusive high-Tc superinductor.” arXiv preprint arXiv:2209.01342 (2022). https://arxiv.org/pdf/2209.01342.
Zettaflops LLC technical report ZF013 accompanies the presentation and appears below. An inline version appears in a concurrent post. The document is also available via arXiv at https://arxiv.org/abs/2504.09229.
Some of my colleagues have expressed interest in the sizing of transistors in reversible logic, so I am posting the result of some simulations I performed in late 2021.
I am posting a PowerPoint at the bottom of this page with simulation output and an explanation. The file is intended to be viewed as an build-up type animation that shows the effect of widening transistors.
Summary of technical issue
CMOS design first and foremost widens transistors to meet timing closure.
Reversible circuits are supposed to be low power, so the baseline assumption is that you should use minimum size transistors everywhere. Such a reversible circuit all will function correctly, but it will not have the lowest dissipation because drops across some of the small transistors will have quadratically growing V2/R losses. So, the lowest energy solution involves making some transistors wider.
Reversible circuits need wider transistors in about the same places as CMOS circuits, namely when driving large capacitive loads or long wires. However, the large transistors reduce dissipation rather than maximize speed. There is an optimal size for both reversible and CMOS transistors, which is where the gate capacitance is about equal to wire capacitance. Gate capacitance larger than this amount causes CMOS to run slower and reversible to dissipate more.
Device variance will cause a reversible gate to dissipate more than the expected amount, but it will still function correctly. This is a better outcome than variance causing a CMOS gate to become slower than expected, miss the setup time of the next latch, and cause data corruption.
Simulation and explanation
The PowerPoint below shows the dissipation of a shift register with a 10 fF wire load. Transistor width is 360 nm, 720 nm, 1.44 μm, 2.88, and μm 5.76 μm. One sees that the reversible advantages shifts to a higher frequency as the transistor becomes wider.
