nRERL is from a South Korean project in the 1999-2005 range [Lim 00] [Kim 05]. The original circuit is based on a 6-phase clock, uses only nFETs, and uses bootstrapping to increase voltage swing. By the time the project matured, there was an 8-phase version that had the ability to “skip” stages [Kim 05]. While 8 clock phases are 1/3 more resource intensive than 6 clock phases, the number of transistors could be reduced by a factor of three.
Simulation code is in the circuit file sNR.cir in the github repository https://github.com/erikdebenedictis.
- [Lim 00] Lim, Joonho, Dong-Gyu Kim, and Soo-Ik Chae. “nMOS reversible energy recovery logic for ultra-low-energy applications.” IEEE Journal of Solid-State Circuits 35.6 (2000): 865-875.
- [Kim 05] Kim, Seokkee, and Soo-Ik Chae. “Complexity reduction in an nRERL microprocessor.” Proceedings of the 2005 international symposium on Low power electronics and design. 2005.