Reversible Computing

Overview

S2LAL was developed by Mike Frank. S2LAL combines important features of 2LAL and SCRL. S2LAL is fully static.

Simulation code is in the circuit file sS2.cir in the github repository https://github.com/erikdebenedictis.

References

• [Frank 21a] Frank, Michael P., et al. “Reversible computing with fast, fully static, fully adiabatic CMOS.” 2020 International Conference on Rebooting Computing (ICRC). IEEE, 2020. https://arxiv.org/ftp/arxiv/papers/2009/2009.00448.pdf.

nRERL is from a South Korean project in the 1999-2005 range [Lim 00] [Kim 05]. The original circuit is based on a 6-phase clock, uses only nFETs, and uses bootstrapping to increase voltage swing. By the time the project matured, there was an 8-phase version that had the ability to “skip” stages [Kim 05]. While 8 clock phases are 1/3 more resource intensive than 6 clock phases, the number of transistors could be reduced by a factor of three.

Simulation code is in the circuit file sNR.cir in the github repository https://github.com/erikdebenedictis.

• [Lim 00] Lim, Joonho, Dong-Gyu Kim, and Soo-Ik Chae. “nMOS reversible energy recovery logic for ultra-low-energy applications.” IEEE Journal of Solid-State Circuits 35.6 (2000): 865-875.
• [Kim 05] Kim, Seokkee, and Soo-Ik Chae. “Complexity reduction in an nRERL microprocessor.” Proceedings of the 2005 international symposium on Low power electronics and design. 2005.

Further introduction TBD.

[Vieri 99] Carlin J. Vieri, “Reversible computer engineering and architecture,” Ph.D. thesis, MIT, 1999. http://hdl.handle.net/1721.1/80144.

Overview

Q2LAL was developed by Erik DeBenedictis as an enhancement on S2LAL that has advantages in some circumstances. Quiet 2-Level Adiabatic Logic (Q2LAL) is like S2LAL but signals with positive-going pulses for A and -A, i.e. A^{^} and -A^{^} in S2LAL notation. The advantage is equal power draw for A=0 and A=1, if engineered correctly, leading to less noise or the circuit being “quiet.”

Simulation code is in the circuit file sQ2.cir in the github repository https://github.com/erikdebenedictis.

Circuit Diagram

The adiabatic amplifier circuit (i.e. unlatched) is shown below.

The circuit requires a clamp signal č_i-1, which can be generated by two transmission gates (four transistors) from clocks. The clamp signal is not dependent on data, so it can be generated once and used in several places.

Connections

Note connection 4 is an optional additional output. If the Extra_buffer parameter is nonzero, the circuit will generate a second adiabatic amplifier with output connected to parameter 4. If Extra_buffer is zero, no transistors are generated and parameter 4 will be a wire that does not go anywhere. The extra buffer is useful for suppressing suppress fault propagation. For example, short circuiting parameter 4 to ground will not affect the output voltage of parameter 3.

1. AT input signal true rail: A_i-1^{^}
2. AC input signal complement rail: -A_i-1^{^}
3. T output signal true rail: Q_i^{^}
4. T2 additional buffered copy of the output signal, with controlled drive, true rail: buf Q_i^{^}
5. C output signal complement rail: Q_i^v
6. pT one of the power-clock phases: phi_i^{^}
7. Cl clamp signal č_i-1: Clmp_i-1^v
8. GND DC power supply ground voltage: GND
9. nsub nFET substrate bias: nsub
10. psub pFET substrate bias: psub

Parameters

1. ini initial state as a voltage, either gg or vv: parameter

Global parameters

PW: width multiplier for drivers on the true rail only

Long_Register: Deprecated debugging flag that removes the clamp on signal AT. Set to 0.

Extra_buffer: If nonzero, causes an additional driver to be created on the true rail with transistor width Clock_Drive. The output of this buffer drives output T2, which is otherwise not connected.

.SUBCKT QAAmp AT AC T T2 C pT Cl GND nsub psub ini='gg' PW=1.002	$ Q2LAL two-rail adiabatic amplifier. Args: AT/C T(2)/C clock clamp GND substrate supplies
.ic V(T)='ini' V(C)='vv-ini'                                $ .ic V(a)={gg} V(a2)=ini
xM0 pT AT T nsub nFET n=1 m=PW                              $ pass gate
xM1 pT AC T psub pFET n=1 m=PW
xM2 pT AC C nsub nFET n=1 m=1                               $ pass gate
xM3 pT AT C psub pFET n=1 m=1
xM4 GND AC T nsub nFET n=1 m=1                              $ clamp
xM5 GND AT C nsub nFET n=1 m=1
xM6 GND Cl T nsub nFET n=1 m=1                              $ clamp
.if (Long_Register=0)
xM7 GND Cl C nsub nFET n=1 m=1
.endif
.if (Extra_Buffer=0)
.else
xM8 pT AT T2 nsub nFET n=1 m='Clock_Drive*PW'               $ pass gate
xM9 pT AC T2 psub pFET n=1 m='Clock_Drive*PW'
xM10 GND AC T2 nsub nFET n=1 m='Clock_Drive'                $ clamp
xM11 GND Cl T2 nsub nFET n=1 m='Clock_Drive'                $ clamp
.endif
.ENDS QAAmp

Typesetting Test Area

The following uses cut-and-paste from EPD’s Word 2003 figures. Render –A_i-1^{^}: -Â_i-1 (so the circumflex diacritical mark works from cut-and-paste). Likewise for cups (caron) č_i-1 (but doesn’t the cee look a little skinny?)

The following is an attempt to render phi₃^{^} by cut-and-paste: f̂₃ (renders as an eff not a phi), but with special character plugin, we get φ₃ (which is correct but not the glyph style we are familiar with).

References

• [DeBenedictis 21a] DeBenedictis, Erik P. “Cryogenic Adiabatic Transistor Circuits for Quantum Computer Control.” 2021 IEEE 14th Workshop on Low Temperature Electronics (WOLTE). IEEE, 2021. https://ar.zettaflops.org/CATC/CATC4QCtl-WOLTE.pdf.
• [DeBenedictis 21b] Quiet 2-Level Adiabatic Logic. Zettaflops, LLC Technical Report ZF009 https://ar.zettaflops.org/CATC/Q2LAL.pdf
• [DeBenedictis 21c] Energy Management for Adiabatic Circuits. Zettaflops, LLC Technical Report ZF008, v1.2, April 15, 2021. https://ar.zettaflops.org/CATC/EMgt4Adia-ZF008-v1.2.pdf.